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W19B320AT/B
8.3 DC Characteristics
8.3.1
CMOS Compatible
PARAMETER
SYM.
TEST CONDITIONS
MIN.
L IMITS
TYP.
MAX.
UNIT
Input Load Current
A9 Input Load Current
Output Leakage Current
I LI
I LIT
I LO
V IN =V SS to V DD , V DD = V DD (Max.)
V DD = V DD (Max.), A9 = 12.5V
V OUT =V SS to V DD , V DD =V DD (Max.)
#CE = V IL, #OE = V IH
5 MHz
-
-
-
-
-
-
-
10
± 1.0
35
± 1.0
16
μ A
μ A
μ A
mA
V DD Active Read Current
(Note 1, 2)
I CC1
Byte Mode
#CE = V IL , #OE = V IH
Word Mode
1 MHz
5 MHz
1 MHz
2
10
2
4
16
4
mA
mA
mA
V DD Active Write Current
(Note 2, 3)
V DD Standby Current (Note2)
V DD Reset Current (Note2)
Automatic Sleep Mode
Current (note 2, 4)
I CC2
I CC3
I CC4
I CC5
#CE = V IL, #OE = V IH, #WE = V IL
#CE = V DD ± 0.3V, #RESET = V DD
± 0.3V
#RESET = V SS ± 0.3V
V IH = V DD ± 0.3V, V IL = V SS ± 0.3V
-
-
-
-
15
0.2
0.2
0.2
30
5
5
5
mA
μ A
μ A
μ A
V DD Active Read-While-
Program Current (note 1, 2)
V DD Active Read-While-
Erase Current (note 1, 2)
V DD Active Program-While-
Erase-Suspended Current
I CC6
I CC7
I CC8
#CE = V IL, #OE = V IH
#CE = V IL, #OE = V IH
#CE = V IL, #OE = V IH
Byte
Word
Byte
Word
-
-
-
-
-
21
21
21
21
17
45
45
45
45
35
mA
mA
mA
(note 2, 5)
ACC Accelerated Program
Current, Word or Byte
Input Low Voltage
Input High Voltage
Voltage for #WP/ACC Sector
Protect/ Unprotect and
Program Acceleration
Voltage for AUTOSELECT
and Temporary Sector
Unprotected
I Acc
V IL
V IH
V HH
V ID
#CE = V IL, #OE = V IH
-
-
V DD =3.0V ± 10%
V DD =3.0V ± 10%
ACC Pin
V DD Pin
-0.5
0.7x V DD
8.5
8.5
5
15
-
-
-
-
10
30
0.8
V DD +0.3
9.5
12.5
mA
mA
V
V
V
V
Output Low Voltage
Output High Voltage
Low V DD Lock-Out Voltage
V OL
V OH1
V OH2
V LKO
I OL = 4.0 mA, V DD = V DD (Min.)
I OH = -2.0 mA, V DD = V DD (Min.)
I OH = -100 μ A, V DD = V DD (Min.)
-
0.85 V DD
V DD - 0.4
2.3
-
-
-
-
0.45
-
-
2.5
V
V
V
Notes:
1.
2.
3.
4.
The I CC current listed is typically less than 2 mA/ MHz, with #OE at V IH .
Maximum I CC specifications are tested with V DD = V DD max.
I CC active while Embedded Erase or Embedded Program is in progress.
Automatic sleep mode enables the low power mode when addresses remain stable for t ACC + 30 ns. Typical sleep mode
current is200 nA.
Publication Release Date: December 27, 2005
- 37 -
Revision A4
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